Most counters follow well-known standard binary counting procedures in which each next higher order bit changes from a "0" to a "1" only after all binary variations of the lower order bits have been used. When this occurs, there is a ripple of bit changes from the lowest order bit through the higher order bits which follows propagation of a "carry" bit through the counter. The delay occasioned by the propagation of the carry is a serious impediment to the operational speed of counters used in high-speed applications, such as in nuclear reaction counting procedures where speeds of 10.sup.8 counts per second or greater are needed.
Designers of binary counters have attempted to address the speed problem by adding special circuitry to enhance the counting process. Various design modifications have been applied to all types of counters, including divide-by-N counters, ripple counters, and synchronous counters.
A divide-by-N counter can count to a given number N. It is continuously clocked and allowed to recycle or rollover to 0 after reaching the Nth count. If the output is taken from the most significant stage of the counter, it provides a pulse that is N times as long as the original clock pulse. The frequency of this output is equal to the frequency of the original clock divided by N.
An example of a divide-by-N counter which has additional circuitry to enhance its speed is shown in U.S. Pat. No. 4,741,004 to Kane entitled "High-Speed Programmable Divide-By-N Counter". Kane '004 employs a plurality of speed enhancement techniques to provide an overall operation corresponding to the speed at which a single-clocked flip-flop is capable of being toggled.
In a ripple counter, the clock ripples through the counter stage by stage, with the output of a lower order stage being provided to the clock of a higher order stage. There must be sufficient time for the clock to ripple through each stage plus any additional gating and decoding time before the next clock pulse can occur. Therefore, the speed of ripple counters is severely limited. Look ahead circuits comprising AND or NAND gates have been used in order to decrease this carry ripple time. However such NAND gates have required a significant amount of die area as the number of counter stages increases. Moreover, this increase in the number of gates which reduces the counting rate.
Synchronous counters are often used to reduce the time delay and glitch problems associated with ripple counters. A synchronous counter has one common clock that is connected to all flip-flop or counter cells. Hence, all flip-flop change at the clock rate regardless of the number of stages. With all stages changing together, glitches are greatly reduced because of the shorter transition time interval. Nevertheless, the clock rate of synchronous counters of the prior art is limited considerably, particular in counters having long word lengths. Each stage must wait to receive a carry from the next lower order bit. The carry, which starts with the lowest order bit, ripples like the clock in the ripple counter through each counter stage. The highest order bit on the counter cannot take on its final value until it receives a carry. In counters with long word lengths, the delay caused by the ripple or propagation of the carry severely limits the speed of the counters.
Modifications to boost speed, such as carry look-ahead circuitry, have been employed in prior art counters. However, with such schemes there is an exponential increase in the number of logic gates required with each additional bit which introduces limits on speed as well as limits on size. In practical applications, use of such circuitry tends to be limited in the number of bits to around five. Furthermore, the layout or design of synchronous counters tend to be complicated, as the structure of high order bit stages are dependent on all next lower order bit cells. This makes it difficult to extend the length of the counter by simply adding additional counters or counting cells.